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copyright ? 2011 cirrus logic, inc. april 2011 all rights reserved ds752pp10 high definition audio decoder dsp family with dual 32-bit engine technology cs4970x4 data sheet preliminary product information this document contains information for a new product. cirrus logic reserves the right to modify this produ ct without notice. http://www.cirrus.com features ? multi-standard 32-bit high-definition audio decoding plus post-processing ? supports high-definition audio formats including: ? dolby digital ? plus ? dolby ? truehd ?dts-hd ? high resolution audio ?dts-hd master audio ? ? dts express ? 5.1 ? supports legacy audio formats and a wide array of post- processing ? dolby digital ? ex, dolby pro logic ? ii, iix, iiz 7.1, dolby headphone 2 ? , dolby virtual speaker 2 ? , dolby volume ? (original), dolby volume 258 (lite), audistry ? ? dts-es 96/24 ? discrete 7.1, dts-es ? discrete 7.1, dts-es ? matrix 6.1, dts neo:6 ? , dts neural surround ? dts surround sensation speaker ? mpeg-2 aac ? lc 5.1 ?srs ? circle surround ii ? , srs circle surround auto, srs circle surround de coder optimized, srs truvolume ? 7.1 (v 2.1.0.0), srs trusurround hd/hd4 ? , srs wow hd ? , srs cs headphone ? , srs circle cinema 3d ? , srs studio sound hd ? ?thx ? ultra2 ? , thx select2 ? ? cirrus logic?s applications library ? cirrus original multi-c hannel surround 2 (coms2), cirrus band xpander ? , cirrus virtualization technology (cvt), cirrus intelligent room calibration 2 (irc2), cirrus bass enhancement (cbe) ? crossbar mixer, signal generator ? advanced post-processors including: 7.1 bass manager quadruple crossover, tone control, 11- band parametric eq, delay, 2:1/4:1 decimator, 1:2/1:4 upsampler ? up to 12 channels of 32-bit serial audio input ? customer software security keys ? 16 ch x 32-bit pcm out with dual 192 khz s/pdif tx ? two spi ? /i 2 c ? ports ? large on-chip x, y, and program ram & rom ? sdram and serial flash memory support the cs4970x4 dsp family is an enhanced version of the cs4953xx dsp family with higher overall performance. in addition to all the mainstream audio processing codes in on- chip rom that the cs4953xx dsp offers, the cs4970x4 device family also supports the decoding of major high-definition audio formats. additionally, the cs4970x4, a dual-core device, performs the high-definition audio decoding on the first core, leaving the second core available for audio post-processing and audio enhancement. the cs4970x4 device supports the most demanding audio post processing requirements. it provides an easy upgrade path to systems cu rrently using the cs495xx or cs4953xx device with minor (or no) hardware and software changes. ordering information see page 25 for ordering information. coyote 32-bit dsp a d m a coyote 32-bit dsp b ext. memory controller p s/pdif x y p x y serial control 1 16 ch pcm audio out serial control 2 parallel control gpio debug stc tmr1 tmr2 pll s/pdif 12 ch pcm audio in
cs4970x4 data sheet 32-bit high definition audio decoder dsp family ds752pp10 2 table of contents 1 documentation strategy .... ................ ................ ................. ................ ................. ................ ......4 2 overview ................... ................. ................ ................ ................. ................ ............... .................4 2.1 migrating from cs495xx(2) to cs4970x4 ..................................................................................... ............ 5 2.2 licensing ................................................................................................................. ................................. 5 3 code overlays ............. ................ ................ ................. ................ ................. ................ .............6 4 hardware functional description ......... .............. .............. .............. .............. .............. .............6 4.1 coyote dsp core ........................................................................................................... .......................... 6 4.1.1 dsp memory .............................................................................................................. .................6 4.1.2 dma controller .......................................................................................................... ..................7 4.2 on-chip dsp peripherals ................................................................................................... ...................... 7 4.2.1 digital audio input port (dai) .......................................................................................... .............7 4.2.2 digital audio output port (dao) ......................................................................................... .........7 4.2.3 serial control port 1 & 2 (i 2 c? or spi?) ...................................................................................7 4.2.4 parallel control port ................................................................................................... .................7 4.2.5 external memory interface ............................................................................................... ...........7 4.2.6 general purpose input/output (gpio) ..................................................................................... ...7 4.2.7 phase-locked loop (pll)-based clock generato r ......................................................................8 4.3 dsp i/o description .................................. ..................................................................... .......................... 8 4.3.1 multiplexed pins ........................................................................................................ ..................8 4.3.2 termination requirements ................................................................................................ ...........8 4.3.3 pads .................................................................................................................... ........................8 4.4 application code se curity ................................................................................................. ....................... 8 5 characteristics and specific ations ................ ................ ................. .............. .............. ............. 8 5.1 absolute maximum ratings .................................................................................................. .................... 8 5.2 recommended operating conditions ............. ............................................................................. ............ 9 5.3 digital dc characteristics ................................................................................................ ........................ 9 5.4 power supply characteristics .............................................................................................. .................... 9 5.5 thermal data (144-pin lqfp) ............................................................................................... ................ 10 5.6 thermal data (128-pin lqfp ) ............................................................................................... ................. 10 5.7 switching characteristics? reset ......................................................................................................... 11 5.8 switching characteristics ? xti ........................................................................................... ................. 11 5.9 switching characteristics ? internal clock .. .............................................................................. ............ 12 5.10 switching characteristics ? serial control port - spi slave mode ..................................................... 12 5.11 switching characteristics ? serial control port - spi master mode ................................................... 13 5.12 switching characteristic s ? serial control port - i 2 c slave mode ...................................................... 14 5.13 switching characteristic s ? serial control port - i 2 c master mode .................................................... 15 5.14 switching characteristics ? para llel control port - intel slave mode ................................................. 16 5.15 switching char acteristics ? parallel control port - motoro la slave mode ......................................... 18 5.16 switching characteristics ? digital audio slave input port ............................................................... .. 20 5.17 switching characteristics ? digital audio output port .................................................................... .... 21 5.18 switching characteristics ? sdram interface .............................................................................. ...... 22 6 ordering information ...... ................. ................ ................ ................. ................ ................ .......25 7 environmental, manufacturing, a nd handling information .............. ............... ........... .........26 8 device pin-out diagram .... ................ ................ ................. ................ ................. ................ ....27 8.1 128-pin lqfp pin-out diagram ...................... ........................................................................ ............... 27 8.2 144-pin lqfp pin-out diagram .................. ........................................................................... ............... 28 9 package mechanical drawings ......... ................ ................. .............. .............. .............. ...........29
cs4970x4 data sheet 32-bit high definition audio decoder dsp family ds752pp10 3 9.1 128-pin lqfp package drawing .............................................................................................. ............. 29 9.2 144-pin lqfp package drawing .............................................................................................. ............. 30 10 revision history .......... ................ ................. ................ ................ ................. ............... ..........31 list of figures figure 1. reset timing ....................................................................................................................... ..................11 figure 2. xti timing .......................................................................................................... ....................................11 figure 3. serial control port - spi slave mode timing ......................................................................... .................13 figure 4. serial control port - spi master mode timing ........................................................................ ................14 figure 5. serial control port - i 2 c slave mode timing ..........................................................................................15 figure 6. serial control port - i 2 c master mode timing ........................................................................................16 figure 7. parallel control port - intel? slave mode read cycle ................................................................ .............17 figure 8. parallel control port - intel slave mode wr ite cycle ................................................................ ..............17 figure 9. parallel control port - motorola? slave mode read cycle timing ...................................................... ....19 figure 10. parallel control port - motorola slave mode write cycle timing ..................................................... ....19 figure 11. digital audio input (dai) port timing dia gram ...................................................................... ...............20 figure 12. dai slave timing diagram ........................................................................................... ........................20 figure 13. digital audio port output timing master mode ....................................................................... ..............21 figure 14. digital audio output timing, slave mode (rel ationship lrclk to sclk) ...........................................22 figure 15. external memory interface - sdram burst read cycle ................................................................. ......23 figure 16. external memory interface - sdram burst write cycle ................................................................ .......23 figure 17. external memory interface - sdram auto re fresh cycle ............................................................... .....24 figure 18. external memory interface - sdram load mode register cycle ........................................................2 5 figure 19. 128-pin lqfp pin-out diagram ........... ............................................................................ ....................27 figure 20. 144-pin lqfp pin-out diagram ........... ............................................................................ ....................28 figure 21. 128-pin lqfp package drawing ....................................................................................... ...................29 figure 22. 144-pin lqfp package drawing ....................................................................................... ...................30 list of tables table 1. cs4970x4 related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 table 2. device and firmware selection guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 3. cs4970x4 dsp memory sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 4. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 5. environmental, manufacturing, & handling information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 6. 128-pin lqfp package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 7. 144-pin lqfp package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
cs4970x4 data sheet 32-bit high definition audio decoder dsp family ds752pp10 4 1 documentation strategy the cs4970x4 data sheet describes the cs4970x4 family of multichannel audio decoders. this document should be used in conjunction with the following docume nts when evaluating or de signing a system around the cs4970x4 family of processors. the scope of the cs4970x4 data sheet is primarily to pr ovide hardware specificatio ns of the cs4970x4 family of devices. this includes hardware functionality, ch aracteristic data, pinout, and packaging information. the intended audience for the cs4970x4 data sheet is the system pcb designer, mcu programmer, and the quality control engineer. 2 overview the cs4970x4 dsp family, combined with cirrus logic?s comprehensive library of audio processing algorithms, enables the development of next-generation high-definition audio solutions. cirrus logic also provides a broad array of digital in terface products and audio converte rs to meet your audio system-level design requirements. note: the cs4970x4 is available in 144-pin and 128- pin lqfp packages. the CS497004-CQZ has since been placed on the not recommended for new designs (nrnd) list and that the cs497024-cvz and cs497014-cvz are the recommended devices. th ese devices are only available in a 128-pin lqfp. the audio processing features of th e cs4970x4 product family are a superset of audio features available in the cs4953xx product family. refer to table 2 on page 5 for the speed and firmware features of the cs4970x4 product family. table 1. cs4970x4 related documentation document name description cs4970x4 data sheet this document cs495314/cs4970x4 system designer?s guide a new consolidated documentation set that includes: ? detailed system design information including typical connection diagrams, boot-procedures, pin descriptions, etc. al so describes use of dsp condenser tool. ? detailed firmware design information including signal processing flow diagrams and control api information an288 - cs4953xx/cs4970x4 firmware user?s manual includes detailed firmware design information including signal processing flow diagrams and control api information
cs4970x4 data sheet 32-bit high definition audio decoder dsp family ds752pp10 5 2.1 migrating from cs495xx(2) to cs4970x4 cs4970x4 was designed to provide an easy upgrade pa th from the cs495xx and cs4953x. although 144-pin versions of the two devices are virtually identical wit h respect to external system connection, there are some small differences the hardware designer should be aware of: ? the pll supply voltage on the cs4970x4 is 3.3v vs. 1.8v on the cs495xx. ? the pll filter topology is simpler when using the cs4970x4 rather than the cs495xx. ? the cs4970x4 adds support for time-division multiplexing (tdm) mode on both audio input and output ports. ? the cs4970x4 does not support external st atic random access memory (sram) operation. ? the cs4970x4 external synchronous dynamic rand om access memory (sdram) bus speed is fixed at 150 mhz vs. the 120 mhz maximum bus speed for the cs495xx. some firmware modules also support a 75 mhz cs4970x4 sdram bus speed. refer to an304 for details. ? the cs4970x4 clkout pin can output xtali or xtali/2. the cs495xx can only output xtali. 2.2 licensing licenses are required for all of the third party audio decoding/processing algorithm s listed below, including the application notes. contact your local cirrus sales representative for more information. table 2. device and firmware selection guide device decode processor (dsp-a) 1 matrix processor module (dsp-a) 1 1. additional processing (mpma, mpmb, vpm , ppm) post any of the hd audio decoders may be limited. contact your cirrus logic fae for the latest concurrency matrix. virtualizer processor module (dsp-b) 1 post processor module (dsp-b) 1 cs497014 300macs stereo pcm (4:1/2:1 down-sampling and 1:2/1:4 u-sampling options) 2 multichannel pcm (4:1/2:1 down-sampling and 1:2/1:4 up-sampling options) 2 dolby digital mpeg-2 aac lc 5.1 dolby digital plus dolby truehd 3 2. downsampling and upsampling functionality is located in the operat ing system. the cirrus decimator (down-sampler) is also available as a separate post-processing module t hat is described in the ap plication note an288ppi. 3. the indicated hd audio decoder algorithms require external sdram. consult your cirrus logic fae for the recommended sdram size for your design. dolby pro logic ii / iix / iiz 7.1 srs circle surround ? ii / circle surround auto / circle surround decoder optimized (stereo in) cirrus original multi-channel surround 2 (effects / reverb processor) crossbar (down-mix / up-mix) (simultaneous process) cirrus virtualizer technology dolby headphone 2 dolby virtual speaker ? 2 dts surround sensation speaker srs cs headphone srs trusurround hd/hd4 app (advanced post- processing) ?tone control ?select 2 ?peq (up to 11 bands) ?delay (speaker to listening position alignment and/or lip sync) ?7.1 bass manager ?audio manager ?4:1/2;1 down-sampling 2 srs truvolume 7.1 multichannel dolby volume multichannel cs497004 300macs cs497024 300macs same as cs49014 + dts, dts-es, dts96/24 dts-hd master audio 3 dts-hd high res audio 3 dts express 5.1 same as cs49014 + dts neo:6, dts neural sound
cs4970x4 data sheet 32-bit high definition audio decoder dsp family ds752pp10 6 3 code overlays the suite of software available for the cs4970x4 family consists of operating systems (os) and a library of overlays. the overlays have been divided into three main groups: decoders, matrix processors, and postprocessors. all software components are defined in the following list: ? os/kernel - encompasses all non-audio processing tasks, including loading data from external memory, processing host messages, calling audio-processing subroutines, auto-detection , error concealment, etc. ? decoders - any module that initially writes data into the audio i/o buffers, e.g. ac-3 ? , dts, pcm, etc. all the decoding/processing algorithms listed require de livery of pcm or iec61937-packed, compressed data via i 2 s- or lj-formatted digital audio to the cs4970x 4 from a/d converters, spdif rx, hdmi rx, etc. ? matrix-processors - any module that processes audio i/o buffer pcm data in-place before the post- processors. generally speaking, these modules alter the number of valid channels in the audio i/o buffer through processes like virtualization (n ? 2 channels) or matrix decoding (2 ? n channels). examples are dolby prologic iix and dts neo:6. ? virtualizer-processor - any module that encodes pcm data into fewer output channels than input channels (n ? 2 channels) with the effect of providing ?phant om? speakers to represent the physical audio channels that were eliminated. examples are dolby headphone 2 and dolby virtual speaker 2. generally speaking, these modules reduce the number of valid channels in the audio i/o buffer. ? post-processors - any module that processes audio i/o buffer pcm data in-place after the matrix processors. examples are bass management, audio man ager, tone control, eq, delay, customer-specific effects, dolby headphone/virtual speaker, etc. the overlay structure reduces the time required to reconfigure the dsp when a processing change is requested. each overlay can be reloaded independentl y without disturbing the other overlays. for example, when a new decoder is selected, the os, matrix-, and post-processors do not need to be reloaded ? only the new decoder (the same is true for the other overlays). 4 hardware functional description 4.1 coyote dsp core the cs4970x4 is a dual-core coyote dsp with separa te x and y data and p code memory spaces. each core is a high-performance, 32-bit, user-programmable, fixed- point dsp that is capable of performing two multiply accumulate (mac) operations per clock cycle. each core has eight 72-bit accumulators, four x- and four y-data registers, and 12 index registers. both dsp cores are coupled to a flexible dma engine. the dma engine can move data between peripherals such as the digital audio input (dai) and digital a udio output (dao), external memory, or any dsp core memory, all without the intervention of the dsp. the dma engine offloads data move instructions from the dsp core, leaving more mips available fo r signal processing instructions. cs4970x4 functionality is controlled by application codes that ar e stored in on-board rom or downloaded to the cs4970x4 from a host mcu or external flash/eeprom. users can choose to use standard audio decoder and post-processor modules which are available from cirrus logic. the cs4970x4 is suitable for audio decoder, audio po st-processor, audio encoder, dvd audio/video player, and digital broadcast decoder applications. 4.1.1 dsp memory each dsp core has its own on-chip data and progra m ram and rom and does not require external memory for any of today?s popular audio algorithms includi ng dolby digital surround ex, aac multichannel, dts-es 96/24, and thx ultra2. however, if the end-system design requires support of the new high-definition audio formats, external sdram will be n eeded to support dolb y truehd and dts-hd master audio. the memory maps for the dsps are as follows. all memory sizes are composed of 32-bit words.
cs4970x4 data sheet 32-bit high definition audio decoder dsp family ds752pp10 7 4.1.2 dma controller the powerful 12-channel dma controller can move data between 8 on-chip resources. each resource has its own arbiter: x, y, and p ram/roms on dsp a; x, y, and p ram/roms on dsp b; external memory; and the peripheral bus. modulo and linear addressing modes are supported, with flexible start address and increment controls. the service interval for each dma channel as well as up to 6 interrupt events, is programmable. 4.2 on-chip dsp peripherals 4.2.1 digital audio input port (dai) the 12-channel (6-line) dai port supports a wide variety of data input formats. the port is capable of accepting pcm or iec61937. up to 32-bit word lengths are suppor ted. additionally, support is provided for audio data input to the dsp via the dai from an hdmi receiver. the port has two independent slave-only clock domains. each data input can be independently assigned to a clock domain. the sample rate of the input clock doma ins can be determined automatically by the dsp, which off-loads the task of monitoring the spdif receiver from the host. a time-stamping feature allows the input data to be sample-rate converted via software. 4.2.2 digital audio output port (dao) there are two dao ports. each port can output 8 channels of up to 32-bit pcm data. the port supports data rates from 32 khz to 192 khz. each port can be config ured as an independent clock domain in slave mode, or the ratio of the two clocks can be set to even multiples of each other in master mode. the two ports can also be ganged together into a single clock domain. each port ha s one serial audio pin that can be configured as a 192-khz spdif transmitter (data with embedded clock on a single line). 4.2.3 serial control port 1 & 2 (i 2 c ? or spi ? ) there are two on-chip serial control ports that are ca pable of operating as master or slave in either i 2 c or spi modes. scp1 defaults to slave operation. it is ded icated for external host-control and supports an external clock up to 50 mhz in spi mode. this high clock sp eed enables very fast code download, control or data delivery. scp2 defaults to master mode and is dedicate d for booting from external serial flash memory or for audio sub-system control. 4.2.4 parallel control port the cs4970x4 parallel port supports both motorola ? and intel ? interfaces. it can be used for both control and data delivery. the parallel port pins ar e multiplexed with serial control port 2 and are available in the 144-pin package. 4.2.5 external memory interface the external memory interface controller supports up to 128 mbits of sdram, using a 16-bit data bus. 4.2.6 general purpose input/output (gpio) many of the cs4970x4 peripheral pins are multiplexed wit h gpio. each gpio can be configured as an output, an input, or an input with in terrupt. each input-pin in terrupt can be conf igured as rising edge, falling edge, active-low, or active-high. table 3. cs4970x4 dsp memory sizes memory type dsp a dsp b x 16k sram, 32k rom 10k sram, 8k rom y 24k sram, 32k rom 16k sram, 16k rom p 8k sram, 32k rom 8k sram, 24k rom
cs4970x4 data sheet 32-bit high definition audio decoder dsp family ds752pp10 8 4.2.7 phase-locked loop (pll)-based clock generator the low-jitter pll generates in teger or fractional multiples of a reference frequency which are used to clock the dsp core and peripherals. through a second pll divi der chain, a dependent clock domain can be output on the dao port for driving audio converters. the cs4970x4 defaults to running from the external reference frequency and can be switched to use the pll output after overlays have been loaded and configured, either through master boot from an external flash or through host control. a bu ilt-in crystal oscillator circuit with a buffered output is provided. the buffered output frequ ency ratio is selectable between 1:1 (default) or 2:1. 4.3 dsp i/o description 4.3.1 multiplexed pins many of the cs4970x4 pins are multi-functional. fo r details on pin functionality please refer to the cs4970x4 system designer?s guide. 4.3.2 termination requirements open-drain pins on the cs4970x4 must be pulled high for proper operation. please refer to the cs4970x4 system designer?s guide to identify which pins are open-drain and what value of pull-up resistor is required for proper operation. mode select pins on the cs4970x4 are used to select the boot mode upon the rising edge of reset. a detailed explanation of termination requirements for each co mmunication mode select pin can be found in the cs4970x4 system designer?s guide . 4.3.3 pads the cs4970x4 i/o operates from the 3.3 v supply and is tolerant within 5 v. 4.4 applicati on code security the external program code may be encrypted by the prog rammer to protect any intellectual property it may contain. a secret, customer-specific key is used to encrypt the program code that is to be stored external to the device. 5 characteristics and specifications note: all data sheet minimum and maximum timing parameters are guaranteed over the rated voltage and temperature. all data sheet typical paramete rs are measured under the following conditions: t=25c, c l = 20 pf, vdd = 1.8 v, vdda = vddio = 3.3 v, gndd = gndio = gnda = 0 v. 5.1 absolute maximum ratings (gndd = gndio = gnda = 0 v; all voltages with respect to 0 v) caution: operation at or beyond these limits may result in pe rmanent damage to the device. normal operation is not guaranteed at these extremes. parameter symbol min max unit dc power supplies: core supply pll supply i/o supply |vdda ? vddio| vdd vdda vddio ?0.3 ?0.3 ?0.3 ? 2.0 3.6 3.6 0.3 v v v v input pin current, any pin except supplies i in ?+/- 10ma input voltage on pll_ref_res v filt -0.3 3.6 v input voltage on i/o pins v inio -0.3 5.0 v storage temperature t stg -65 150 c
cs4970x4 data sheet 32-bit high definition audio decoder dsp family ds752pp10 9 5.2 recommended op erating conditions (gndd = gndio = gnda = 0 v; all voltages with respect to 0 v) note: it is recommended that the 3.3 v io supply come up ah ead of or simultaneously with the 1.8 v core supply. 5.3 digital dc characteristics (measurements performed under static conditions.) 5.4 power supply characteristics (measurements performed under operating conditions.) parameter symbol min typ max unit dc power supplies: core supply pll supply i/o supply |vdda ? vddio| vdd vdda vddio 1.71 3.13 3.13 1.8 3.3 3.3 0 1.89 3.46 3.46 v v v v ambient operating temperature commercial grade (cqz/cvz) t a 0 +25 + 70 c commercial t j 0+125oc parameter symbol min typ max unit high-level input voltage v ih 2.0 ? ? v low-level input voltage, except xti v il ??0.8 v low-level input voltage, xti v ilxti ??0.6 v input hysteresis v hys ?0.4 ? v high-level output voltage (i o = -4ma), except xti, sdram pins v oh vddio * 0.9 ? ? v low-level output voltage (i o = 4ma), except xti, sdram pins v ol ??vddio * 0.1v sdram high-level output voltage (i o = -8ma) v oh vddio * 0.9 ? ? v sdram low-level output voltage (i o = 8ma) v ol ??vddio * 0.1v input leakage current (all digital pins with internal pull-up resistors disabled) i in ?? 5 a input leakage current (all digital pins with internal pull-up resistors enabled, and xti) i in-pu ?? 70 a parameter min typ max unit power supply current: core and i/o operating: vdd 1 pll operating: vdda with external memory and most ports operating: vddio 1.dependent on application firmware and dsp clock speed. ? ? ? 350 3.5 120 ? ? ? ma ma ma
cs4970x4 data sheet 32-bit high definition audio decoder dsp family ds752pp10 10 5.5 thermal data (144-pin lqfp) 5.6 thermal data (128-pin lqfp) notes: 1. two-layer board is specified as a 76 mm x 114 mm, 1.6 mm thi ck fr-4 material with 1-oz. copper covering 20% of the top and bottom layers. 2. four-layer board is specified as a 76 mm x 114 mm, 1.6 mm thick fr-4 material with 1-oz. copper covering 20% of the top and bottom layers and 0.5-oz. copper covering 90% of the internal power plane and ground plane layers. 3. to calculate the die temperatur e for a given power dissipation j = ambient temperature + [ (power dissipation in watts) * ja ] 4. to calculate the case temperature for a given power dissipation c = j - [ (power dissipation in watts) * jt parameter symbol min typ max unit thermal resistance (junction to ambient) two-layer board 1 four-layer board 2 ja ? ? 48 40 ? ? c / watt thermal resistance (junction to top of package) two-layer board 1 four-layer board 2 jt ? ? .39 .33 ? ? c / watt parameter symbol min typ max unit thermal resistance (junction to ambient) two-layer board 1 four-layer board 2 ja ? ? 53 44 ? ? c / watt thermal resistance (junction to top of package) two-layer board 1 four-layer board 2 jt ? ? .45 .39 ? ? c / watt
cs4970x4 data sheet 32-bit high definition audio decoder dsp family ds752pp10 11 5.7 switching ch aracteristics?reset figure 1. reset timing 5.8 switching char acteristics ? xti figure 2. xti timing parameter symbol min max unit reset minimum pulse width low t rstl 1? s all bidirectional pins high-z after reset low t rst2z ? 100 ns configuration pins setup before reset high t rstsu 50 ? ns configuration pins hold after reset high t rsthld 20 ? ns parameter symbol min max unit external crystal operating frequency 1 1. part characterized with the followi ng crystal frequency values: 12.288 and 24.576 mhz. f xtal 12.288 24.576 mhz xti period t clki 41 81.4 ns xti high time t clkih 16.4 ? ns xti low time t clkil 16.4 ? ns external crystal load capacitance (parallel resonant) 2 2. c l refers to the total load capacitance as specified by the crystal manufacturer. crystals which require a c l outside this range should be avoided. the crystal oscillator circuit design shoul d follow the crystal manufacturer?s recommendation for load capac itor selection. c l 10 18 pf external crystal equivalent series resistance esr ? 50 reset# t rst2z t rstl t rstsu t rsthld hs[3:0] all bidirectional pins t clkih t clkil t clki xti
cs4970x4 data sheet 32-bit high definition audio decoder dsp family ds752pp10 12 5.9 switching characteris tics ? internal clock 5.10 switching character istics ? serial control port - spi slave mode parameter symbol min max unit internal dclk frequency 1 1. after initial power-on reset, f dclk = f xtal . after initial kick-start commands, the pll is locked to max f dclk and remains locked until the next power-on reset. f dclk ? ?mhz CS497004-CQZ CS497004-CQZr cs497024-cvz cs497024-cvzr cs497014-cvz cs497014-cvzr cs497024-cvz cs497024-cvzr f xtal 150 internal dclk period 1 dclkp ? ? ns CS497004-CQZ CS497004-CQZr cs497024-cvz cs497024-cvzr cs497014-cvz cs497014-cvzr cs497024-cvz cs497024-cvzr 6.7 1/f xtal parameter symbol min typical max units scp_clk frequency 1 1. the specification f spisck indicates the maximum speed of the hardware. the system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application. flow control using the scp_ bsy pin should be implemented to prevent overflow of the in put data buffer. at boot the maximum speed is fxtal/3. f spisck ?? 25mhz scp_cs falling to scp_clk rising t spicss 24 ? ? ns scp_clk low time t spickl 20 ? ? ns scp_clk high time t spickh 20 ? ? ns setup time scp_mosi input t spidsu 5? ?ns hold time scp_mosi input t spidh 5? ?ns scp_clk low to scp_ miso output valid t spidov ?? 11ns scp_clk falling to scp_irq rising t spiirqh ? ? 20 ns scp_cs rising to scp_irq falling t spiirql 0? ?ns scp_clk low to scp_cs rising t spicsh 24 ? ? ns scp_cs rising to scp_miso output high-z t spicsdz ?20 ?ns scp_clk rising to scp_bsy falling t spicbsyl ?3 * dclkp+20 ? ns
cs4970x4 data sheet 32-bit high definition audio decoder dsp family ds752pp10 13 figure 3. serial control po rt - spi slave mode timing 5.11 switching character istics ? serial control port - spi master mode parameter symbol min typical max units scp_clk frequency 1, 2 1. the specification f spisck indicates the maximum speed of the hardware. the system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application. 2. see section 5.8. 3. scp_clk period refers to the period of scp_clk as being used in a given application. it does not refer to a tested parameter. f spisck ?? f xtal /2 mhz scp_cs falling to scp_clk rising 3 t spicss ? 11*dclkp + (scp_clk period)/2 ?ns scp_clk low time t spickl 18 ? ? ns scp_clk high time t spickh 18 ? ? ns setup time scp_miso input t spidsu 11 ? ? ns hold time scp_miso input t spidh 5? ?ns scp_clk low to scp_ mosi output valid t spidov ?? 11ns scp_clk low to scp_cs falling t spicsl 7? ?ns scp_clk low to scp_cs rising t spicsh ? 11*dclkp + (scp_clk period)/2 ?ns bus free time between active scp_cs t spicsx ? 3*dclkp ? ns scp_clk falling to scp_mosi output high-z t spidz ? ? 20 ns scp_bsy# scp_cs# scp_clk scp_mosi scp_miso scp_irq# 0 12670 56 7 t spicss t spickl t spickh t spidsu t spidh t spidov a6 a5 a0 r/w msb lsb msb lsb t spicsh t spibsyl t spiirql t spiirqh f spisck t spicsdz
cs4970x4 data sheet 32-bit high definition audio decoder dsp family ds752pp10 14 . figure 4. serial control port - spi master mode timing 5.12 switching char acteristics ? serial control port - i 2 c slave mode parameter symbol min typical max units scp_clk frequency 1 1. the specification f iicck indicates the maximum speed of the hardware. t he system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application. flow control using the scp_ bsy pin should be implemented to prevent overflow of the input data buffer. f iicck ?? 400khz scp_clk low time t iicckl 1.25 ? ? s scp_clk high time t iicckh 1.25 ? ? s scp_sck rising to scp_sda risi ng or falling for start or stop condition t iicckcmd 1.25 ? ? s start condition to scp_clk falling t iicstscl 1.25 ? ? s scp_clk falling to stop condition t iicstp 2.5 ? ? s bus free time between stop and start conditions t iicbft 3? ?s setup time scp_sda input valid to scp_clk rising t iicsu 100 ? ? ns hold time scp_sda inpu t after scp_clk falling t iich 20 ? ? ns scp_clk low to scp_sda out valid t iicdov ?? 18 ns scp_clk falling to scp_irq rising t iicirqh ??3 * dclkp + 40 ns nak condition to scp_irq low t iicirql ?3 * dclkp + 20 ? ns scp_clk rising to scb_bsy low t iicbsyl ?3 * dclkp + 20 ? ns ee_cs# scp_clk scp_miso scp_mosi 0 12670 56 7 t spicss t spickl t spickh t spidsu t spidh t spidov a6 a5 a0 r/w msb lsb msb lsb t spicsh t spicsx f spisck t spidz t spicsl
cs4970x4 data sheet 32-bit high definition audio decoder dsp family ds752pp10 15 figure 5. serial control port - i 2 c slave mode timing 5.13 switching char acteristics ? serial control port - i 2 c master mode parameter symbol min max units scp_clk frequency 1 1. the specification f iicck indicates the maximum speed of the hardware. t he system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application. f iicck ? 400 khz scp_clk low time t iicckl 1.25 ? s scp_clk high time t iicckh 1.25 ? s scp_sck rising to scp_sda rising or falling for start or stop condition t iicckcmd 1.25 ? s start condition to scp_clk falling t iicstscl 1.25 ? s scp_clk falling to stop condition t iicstp 2.5 ? s bus free time between stop and start conditions t iicbft 3?s setup time scp_sda input valid to scp_clk rising t iicsu 100 ? ns hold time scp_sda inpu t after scp_clk falling t iich 20 ? ns scp_clk low to scp_sda out valid t iicdov ?36ns scp_bsy# scp_clk scp_sda scp_irq# 01 67801 7 t iicckl t iicckh t iicsu t iich a6 a0 r/w ack lsb t iicirqh t iicirql 8 ack msb t iicstp 6 t iiccbsyl t iicdov t iicbft t iicstscl t iicckcmd f iicck t iicckcmd t iicf t iicr
cs4970x4 data sheet 32-bit high definition audio decoder dsp family ds752pp10 16 figure 6. serial control port - i 2 c master mode timing 5.14 switching character istics ? parallel control port - intel slave mode parameter symbol min typical max unit address setup before pcp_cs and pcp_rd low or pcp_cs and pcp_wr low t ias 5??ns address hold time after pcp_cs and pcp_rd low or pcp_cs and pcp_wr high t iah 5??ns read delay between pcp_rd then pcp_cs low or pcp_cs then pcp_rd low t icdr 0??ns data valid after pcp_cs and pcp_rd low t idd ??18ns pcp_cs and pcp_rd low for read t irpw 24 ? ? ns data hold time after pcp_cs or pcp_rd high t idhr 8??ns data high-z after pcp_cs or pcp_rd high t idis ??18ns pcp_cs or pcp_rd high to pcp_cs and pcp_rd low for next read 1 t ird 30 ? ? ns pcp_cs or pcp_rd high to pcp_cs and pcp_wr low for next write 1 t irdtw 30 ? ? ns pcp_rd rising to pcp_irq rising t irdirqhl ??12ns write delay between pcp_wr then pcp_cs low or pcp_cs then pcp_wr low t icdw 0??ns data setup before pcp_cs or pcp_wr high t idsu 8??ns pcp_cs and pcp_wr low for write t iwpw 24 ? ? ns data hold after pcp_cs or pcp_wr high t idhw 8??ns scp_clk scp_sda 01 67801 7 t iicckl t iicckh t iicsu t iich a6 a0 r/w ac k lsb 8 ack msb t iicstp 6 t iicdov t iicb t iicstscl t iicckcmd f iicck t iicckcmd t iicf t iicr
cs4970x4 data sheet 32-bit high definition audio decoder dsp family ds752pp10 17 figure 7. parallel control port - intel ? slave mode read cycle figure 8. parallel control port - intel slave mode write cycle pcp_cs or pcp_wr high to pcp_cs and pcp_rd low for next read 1 t iwtrd 30 ? ? ns pcp_cs or pcp_wr high to pcp_cs and pcp_wr low for next write 1 t iwd 30 ? ? ns pcp_wr rising to pcp_bsy falling t iwrbsyl ? 2*dclkp + 20 ? ns 1. the system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application. hardware handshaking on the pcp_ bsy pin/bit should be observed to prevent overflowing the input data buffer. cs4953x4/cs4970x4 system designer?s guide should be consulted for the firmware speed limitations. parameter symbol min typical max unit pcp_a[3:0] pcp_d[7:0] t ias t icdr t iah t idd t irpw t idhr t idis t ird t irdtw pcp_cs# pcp_wr# pcp_rd# pcp_irq# t irdirqh lsp msp t ias t icdw t iah t iwpw t idhw t iw d t iwtrd t idsu t iwrbsyl pcp_d[7:0] pcp_cs# pcp_wr# pcp_rd# pcp_a[3:0] pcp_bsy# lsp msp
cs4970x4 data sheet 32-bit high definition audio decoder dsp family ds752pp10 18 5.15 switching characteris tics ? parallel control po rt - motorola slave mode parameter symbo lmin typical maxunit address setup before pcp_cs and pcp_ds low t mas 5??ns address hold time after pcp_cs and pcp_ds low t mah 5??ns read delay between pcp_ds then pcp_cs low or pcp_cs then pcp_ds low t mcdr 0??ns data valid after pcp_cs and pcp_ds low with pcp_r/w high t mdd ? ? 19 ns pcp_cs and pcp_ds low for read t mrpw 24 ? ? ns data hold time after pcp_cs or pcp_ds high after read t mdhr 8??ns data high-z after pcp_cs or pcp_ds high after read t mdis ? ? 18 ns pcp_cs or pcp_ds high to pcp_cs and pcp_ds low for next read 1 1. the system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application. hardware handshaking on the pcp_ bsy pin/bit should be observed to prevent overflowing the input data buffer. cs4953x4/cs4970x4 system designer?s guide should be consulted for the firmware speed limitations. t mrd 30 ? ? ns pcp_cs or pcp_ds high to pcp_cs and pcp_ds low for next write 1 t mrdtw 30 ? ? ns pcp_rw rising to pcp_irq falling t mrwirqh ? ? 12 ns write delay between pcp_ds then pcp_cs low or pcp_cs then pcp_ds low t mcdw 0??ns data setup before pcp_cs or pcp_ds high t mdsu 8??ns pcp_cs and pcp_ds low for write t mwpw 24 ? ? ns pcp_r/w setup before pcp_cs and pcp_ds low t mrwsu 24 ? ? ns pcp_r/w hold time after pcp_cs or pcp_ds high t mrwhld 8??ns data hold after pcp_cs or pcp_ds high t mdhw 8??ns pcp_cs or pcp_ds high to pcp_cs and pcp_ds low with pcp_r/w high for next read 1 t mwtrd 30 ? ? ns pcp_cs or pcp_ds high to pcp_cs and pcp_ds low for next write 1 t mwd 30 ? ? ns pcp_rw rising to pcp_bsy falling t mrwbsyl ?2*dclkp + 20?ns
cs4970x4 data sheet 32-bit high definition audio decoder dsp family ds752pp10 19 figure 9. parallel control port - motorola ? slave mode read cycle timing figure 10. parallel control port - mo torola slave mode write cycle timing t mas t mcdr t mah t mdd t mrpw t mdhr t mdis t mrd t mrdtw t mrwsu t mrwhld pcp_a[3:0] pcp_ad[7:0] pcp_cs# pcp_wr# pcp_ds# pcp_irq# t mrwirqh lsp msp t mas t mdsu t mdhw t mwd t mwtrd t mwpw t mcdw t mrwsu t mrwhld mah t pcp_a[3:0] pcp_ad[7:0] pcp_cs# pcp_wr# pcp_ds# pcp_irq# t mrwirql lsp msp
cs4970x4 data sheet 32-bit high definition audio decoder dsp family ds752pp10 20 5.16 switching char acteristics ? digital audio slave input port note: in these diagrams, falling edge is the inactive edge of dai_sclk. figure 11. digital audio input (dai) port timing diagram figure 12. dai slave timing diagram parameter symbol min max unit dai_sclk period t daiclkp 40 ? ns dai_sclk duty cycle ?4555% dai_lrclk transition from dai_sclk active edge t daisstlr 10 ? ns dai_sclk active edge from dai_lrclk transition t daislrts 10 ? ns setup time dai_datan t daidsu 10 ? ns hold time dai_datan t daidh 5?ns dai_sclk dai_datan t daidh t daidsu dai_sclk dai_lrclk dain_datan t daislrts t daiclkp dai_sclk dai_lrclk t daisstlr t daiclkp dain_datan
cs4970x4 data sheet 32-bit high definition audio decoder dsp family ds752pp10 21 5.17 switching characteristics ? digital audio output port figure 13. digital audio port output timing master mode parameter symbol min max unit dao_mclk period t daomclk 40 ? ns dao_mclk duty cycle ? 45 55 % dao_sclk period for master or slave mode 1 1. master mode timing specifications ar e characterized, not production tested. t daosclk 40 ? ns dao_sclk duty cycle for master or slave mode 1 ? 40 60 % master mode (output a1 mode) 1,2 2. master mode is defined as the cs4970x4 driving both dao_sclk, dao_lrclk. when mclk is an in put, it is divided to produce dao_sclk, dao_lrclk. dao_sclk delay from dao_mclk rising edge, dao_mclk as an input t daomsck ? 19 ns dao_sclk delay from dao_lrclk transition 3 t daomlrts ? 8ns dao_lrclk delay from dao_sclk transition 3 3. this timing parameter is defined from the non-active edge of da o_sclk. the active edge of dao_sclk is the point at which the data is valid. t daomstlr ? 8ns dao1_data[3..0], dao2_data[1..0] delay from dao_sclk transition 3 t daomdv ? 10 ns slave mode (output a0 mode) 4 4. slave mode is defined as dao_sclk, da o_lrclk driven by an external source. dao_sclk active edge to dao_lrclk transition t daosstlr 10 ? ns dao_lrclk transition to dao_sclk active edge t daoslrts 10 ? ns dao_dx delay from dao_sclk inactive edge t daosdv ?11ns dao_mclk dao_sclk dao_lrclk daon_datan t daomlclk t daomsck t daomdv t daomlrts dao_mclk dao_sclk dao_lrclk daon_datan t daomlclk t daomsck t daomdv t daomlrts note : in these diagrams, falling edge is the inactive edge of dao_sclk.
cs4970x4 data sheet 32-bit high definition audio decoder dsp family ds752pp10 22 figure 14. digital audio output timing, slave mode (relationship lrclk to sclk) 5.18 switching character istics ? sdram interface refer to figure 15 through figure 18 . (sd_clkout = sd_clkin) parameter symbol min typical max unit sd_clkin high time t sdclkh 2.3 ?? ns sd_clkin low time t sdclkl 2.3 ?? ns sd_clkout rise/fall time t sdclkrf ?? 1ns sd_clkout frequency ?? 150 ? mhz sd_clkout duty cycle ? 45 ? 55 % sd_clkout rising edge to signal valid t sdcmdv ?? 3.8 ns signal hold from sd_clkout rising edge t sdcmdh ? 1.1 ? ns sd_clkout rising edge to sd_dqmn valid t sddqv ? 3.8 ? ns sd_dqmn hold from sd_clkout rising edge t sddqh 1.38 ?? ns sd_data valid setup to sd_clkin rising edge t sddsu 1.3 ?? ns sd_data valid hold to sd_clkin rising edge t sddh 1.38 ?? ns sd_clkout rising edge to addrn valid t sdav ? 3.8 ? ns dao_sclk dao_lrclk dao_dx t daoslrts t daosclk dao_sclk dao_lrclk t daosstlr t daosdv t daosclk dao_dx note: in these diagrams, falling edge is the inac tive edge of dao_sclk
cs4970x4 data sheet 32-bit high definition audio decoder dsp family ds752pp10 23 figure 15. external memory interface - sdram burst read cycle figure 16. external memory inte rface - sdram burst write cycle sd_clkout sd_cs# sd_ras# sd_cas# sd_we# sd_dqmn sd_an sd_dn t sddsu t sdclkrf t sdcmdv t sdav t sddqv t sdcmdh t sddh t sddqh cas=2 lsp0 msp0 lsp3 msp 3 sd_clkin t sdclkl t sdclkh 00 11 lsp1 msp1 lsp2 msp2 sd_clkout sd_cs# sd_ras# sd_cas# sd_we# t sdcmdv t sdcmdh sd_dn lsp0 msp0 lsp1 msp1 lsp2 msp2 lsp3 msp3 sd_an sd_dqmn t sddqh 00 11 t sddqv t sdav
ds752pp10 24 cs4970x4 data sheet 32-bit high definition audio decoder dsp family figure 17. external memory inte rface - sdram auto refresh cycle sd_clkout sd_cs# sd_ras# sd_cas# sd_we# sd_dqmn sd_an sd_dn t sdcmdv t sdcmdh t sdcmdv
ds752pp10 25 cs4970x4 data sheet 32-bit high definition audio decoder dsp family figure 18. external memo ry interface - sdram load mode register cycle 6 ordering information the cs4970x4 family part nu mber is described as follows: cs497nni-xyz where nn - product number variant i - rom id number x - product grade y - package type z - lead (pb) free sd_clkout sd_cs# sd_ras# sd_cas# sd_we# sd_dqmn sd_an sd_dn opcode t sdcmdv t sdcmdh
cs4970x4 data sheet 32-bit high definition audio decoder dsp family ds752pp10 26 note: please contact the factory for availabilit y of the -d (automotive grade) package. 7 environmental, manufacturing, and handling information * msl (moisture sensitivity level) as specified by ip c/jedec j-std-020. table 4. ordering information part no. status grade temp. range package CS497004-CQZ eol commercial 0 to +70 c 144-pin lqfp CS497004-CQZr 1 1. r = tape and reel eol commercial 0 to +70 c cs497014-cvz active commercial 0 to +70 c 128-pin lqfp cs47014-cvzr 1 active commercial 0 to +70 c cs497024-cvz active commercial 0 to +70 c 128-pin lqfp cs497024-cvzr 1 active commercial 0 to +70 c table 5. environmental, manufact uring, & handling information model number peak reflow temp msl rating* max floor life CS497004-CQZ 260 c 3 7 days CS497004-CQZr 260 c 3 7 days cs497014-cvz 260 c 3 7 days cs47014-cvzr 260 c 3 7 days cs497024-cvz 260 c 3 7 days cs497024-cvzr 260 c 3 7 days
cs4970x4 data sheet 32-bit high definition audio decoder dsp family ds752pp10 27 8 device pin-out diagram 8.1 128-pin lqfp pin-out diagram figure 19. 128-pin lqfp pin-out diagram gpio2 gpio1 gpio0, ee_cs# xto vdd7 gnd7 vddio7 xti gndio7 gnda pll_ref_res vdda (3.3v) vdd8 gnd8 gpio13, dai1_data2, tm2, dsd2 gpio14, dai1_data3, tm3, dsd3 dai1_data0, tm0, dsd0 gpio12, dai1_data1, tm1, dsd1 gpio6, pcp_cs#, scp2_cs# gpio38, pcp_wr# / ds#, scp2_clk vdd6 gnd6 gpio10, pcp_a2 / a10, scp2_mosi gpio8, pcp_irq#, scp2_irq# gpio37, scp1_bsy#, pcp_bsy# vddio6 gpio11, pcp_a3, as#, scp2_miso / sda gndio6 gpoi9, scp1_irq# gpio34, scp1__miso / sda gpio33, scp1_mosi gpio35, scp1_clk vdd5 vddio5 gnd5 gndio5 sd_cas# sd_ras# sd_a3, ext_a3 sd_a2, ext_a2 sd_a1, ext_a1 sd_a0, ext_a0 sd_a10, ext_a10 sd_a11, ext_a11 vdd4 gnd4 sd_cs# sd_a4, ext_a4 sd_a5, ext_a5 sd_a6, ext_a6 sd_a7, ext_a7 sd_a8, ext_a8 sd_clken sd_a9, ext_a9 vddio4 gndio4 sd_clkout sd_clkin sd_d10, ext_d10 sd_d11, ext_d11 sd_d12, ext_d12 vdd3 gnd3 sd_d13, ext_d13 sd_d14, ext_d14 sd_d15, ext_d15 sd_dqm1 sd_d7, ext_d7 sd_d6, ext_d6 vddio3 gndio3 sd_d5, ext_d5 sd_dqm0 sd_d4, ext_d4 sd_d3, ext_d3 sd_d2, ext_d2 gpio17, dao1_data3 / xmta gpio15, dao1_data1, hs1 dao1_data0, hs0 dao1_lrclk dai1_lrclk, dsd4 dao_mclk gpio20, dao2_data2 dai1_sclk, dsd_clk vdd1 gnd1 dao1_sclk gpio16, dao1_data2, hs2 gpio23, dao2_lrclk reset# vddio1 gpio22, dao2_sclk gndio1 gpio18, dao2_data0, hs3 gpio19, dao2_data1, hs4 vdd2 gnd2 gpio26, dao2_data3 / xmtb vddio2 gndio2 sd_we# sd_d0, ext_d0 sd_d1, ext_d1 sd_d8, ext_d8 sd_d9, ext_d9 sd_a12, ext_a12 sd_ba1, ext_a14 sd_ba0, ext_a13 gpio7, scp1_cs#, iowait vddio8 gndio8 ext_a15 ext_a16 ext_a17 ext_a18 ext_a19 ext_cs1# ext_oe# ext_we# gpio3, ddac test dbda dbck xtal_out gpio43, bdi_clk, dai2_sclk gpio42, bdi_req# , dai2_lrclk, pcp_irq# / bsy# bdi_data, dai2_data, dsd5 ext_cs2# 10 15 20 25 30 5 35 1 125 120 115 110 105 95 90 85 80 75 70 65 100 40 45 50 55 60 cs497xx4 128-pin lqfp
cs4970x4 data sheet 32-bit high definition audio decoder dsp family ds752pp10 28 8.2 144-pin lqfp pin-out diagram figure 20. 144-pin lqfp pin-out diagram gpio11, pcp_a3, as#, scp2_miso / sda sd_a11, ext_a11 gpio26 gpio21, dao2_data3 / xmtb sd_a12, ext_a12 gpio42, bdi_req# , dai2_lrclk, pcp_irq# / bsy# 113 116 119 122 126 129 130 133 136 139 109 110 115 120 125 135 140 144 cs497xx4 144-pin lqfp gpio25, ee_cs# gpio24 gpio31 sd_d7, ext_d7 sd_d6, ext_d6 sd_d5, ext_d5 sd_dqm0 sd_d4, ext_d4 sd_d3, ext_d3 sd_d2, ext_d2 gpio17, dao1_data3 / xmta gpio15, dao1_data1, hs1 dao1_data0, hs0 dao1_lrclk dao_mclk gpio20, dao2_data2 vdd1 gnd1 dao1_sclk gpio16, dao1_data2, hs2 gpio23, dao2_lrclk vddio1 gpio22, dao2_sclk gndio1 gpio18, dao2_data0, hs3 gpio19, dao2_data1, hs4 vdd2 gnd2 vddio2 gndio2 gpio28, ddac gpio29, xmta_in test dbda dbck 1 5 9 10 13 18 21 24 27 33 36 15 25 30 35 sd_a3, ext_a3 sd_a2, ext_a2 sd_a1, ext_a1 sd_a0, ext_a0 vdd4 gnd4 sd_a4, ext_a4 sd_a5, ext_a5 sd_a6, ext_a6 sd_a7, ext_a7 sd_a8, ext_a8 sd_clken sd_a9, ext_a9 vddio4 gndio4 sd_clkout sd_clkin sd_d10, ext_d10 sd_d11, ext_d11 sd_d12, ext_d12 vdd3 gnd3 sd_d13, ext_d13 sd_d14, ext_d14 sd_d15, ext_d15 sd_dqm1 vddio3 gndio3 sd_d0, ext_d0 sd_d1, ext_d1 sd_d8, ext_d8 sd_d9, ext_d9 ext_cs2# ext_we# 69 66 63 60 57 54 47 44 37 40 45 50 55 65 70 72 gpio39, pcp_cs#, scp2_cs# gpio38, pcp_wr# / ds#, scp2_clk vdd6 gpio40, pcp_rd# / rw# gnd6 gpio10, pcp_a2 / a10, scp2_mosi gpio41, pcp_irq#, scp2_irq# gpio37, scp1_bsy#, pcp_bsy# vddio6 gndio6 gpoi36, scp1_irq# gpio34, scp1__miso / sda gpio33, scp1_mosi gpio35, scp1_clk vdd5 vddio5 gnd5 gndio5 sd_cas# sd_ras# sd_a10, ext_a10 sd_cs# reset# sd_we# sd_ba1, ext_a14 sd_ba0, ext_a13 gpio32, scp1_cs#, iowait ext_a15 ext_a16 ext_a17 ext_a18 ext_a19 ext_cs1# ext_oe# gpio30, xmtb_in 101 98 94 91 86 83 76 73 75 80 85 90 95 100 105 108 gpio1, pcp_ad1 / d1 gpio0, pcp_ad0 / d0 xto vdd7 gnd7 vddio7 xti gndio7 gnda nc pll_ref_res vdda (3.3v) vdd8 gnd8 gpio13, dai1_data2, tm2, dsd2 gpio14, dai1_data3, tm3, dsd3 dai1_data0, tm0, dsd0 gpio12, dai1_data1, tm1, dsd1 gpio2, pcp_ad2 / d2 gpio3, pcp_ad3 / d3 gpio4, pcp_ad4 / d4 gpio5, pcp_ad5 / d5 gpio6, pcp_ad6 / d6 gpio7, pcp_ad7 / d7 gpio9, pcp_a1 / a9 dai1_lrclk, dsd4 dai1_sclk, dsd_clk vddio8 gndio8 gpio8, pcp_a0 / a8 gpio27 xtal_out gpio43, bdi_clk, dai2_sclk bdi_data, dai2_data, dsd5
cs4970x4 data sheet 32-bit high definition audio decoder dsp family ds752pp10 29 9 package mechanical drawings 9.1 128-pin lqfp package drawing figure 21. 128-pin lqfp package drawing table 6. 128-pin lqfp package characteristics dim millimeters inches min nom max min nom max a ? ? 1.60 ? ? .063? a1 0.05 ? 0.15 .002? ? .006? b 0.17 0.22 0.27 .007? .009? .011? d 22.00 bsc .866? d1 20.00 bsc .787? e 16.00 bsc .630? e1 14.00 bsc .551? e 0.50 bsc .020? q 0 3.5 7 0 3.5 7 l 0.45 0.60 0.75 .018? .024? .030? l1 1.00 ref .039? ref tolerances of form and position ddd 0.08 .003? d1 d e1 e 1 e l b a1 a
cs4970x4 data sheet 32-bit high definition audio decoder dsp family ds752pp10 30 9.2 144-pin lqfp package drawing figure 22. 144-pin lqfp package drawing table 7. 144-pin lqfp package characteristics dim millimeters inches min nom max min nom max a ? ? 1.60 ? ? .063? a1 0.05 ? 0.15 .002? ? .006? b 0.17 0.22 0.27 .007? .009? .011? d 22.00 bsc .866? d1 20.00 bsc .787? e 22.00 bsc .866? e1 20.00 bsc .787? e 0.50 bsc .020? q 0 ? 7 0 ? 7 l 0.45 0.60 0.75 .018? .024? .030? l1 1.00 ref .039? ref tolerances of form and position ddd 0.08 .003? d1 d e l b a1 a l1 notes: controlling dimension is millimeter. dimensioning and tolerancing per asme y14.5m-1994. e1 e m b seating plane ddd b
cs4970x4 data sheet 32-bit high definition audio decoder dsp family ds752pp10 31 10 revision history revision date changes a1 feb 2007 advance release. pp1 may 2007 removed advanced product watermark, corrected logo, and added ?preliminary product information? on first page and modified legal information to reflect preliminary product status. pp2 july 2007 added notice about status of dts-hd license on page 1 and 7. pp3 oct 2007 updated the tspidsu, tspickl, and tspickh timing parameters for master mode spi. this applies to both spi ports. removed dts-hd license notice inserted in version pp2. the license for the dts-hd decoder is now in place. updated pin assignments in 144-pin lqfp pin-out diagram, removing ee_cs from pin 7 and adding ee_cs to pin 25. pp4 december 20, 2007 updated dao timing specifications and ti ming diagrams. changed product naming conventions in table 4 and table 5 . changed references to cs4970x4 hardware user?s manual to cs4970x4 system designer?s guide. changed references to cs4970x4 firmware user?s manual to cs4970x4 system designer?s guide pp5 may 28, 2008 added 128-pin lqfp pin-out and package drawings. changed part numbering in section 6 and section 7 added device and firmware selection guide in table 2 . pp6 august 4, 2008 added typical crystal frequency values in table footnote 1 and the max and min values of f xtal in section 5.8. redefined master mode clock speed for scp_clk in section 5.11. redefined dc leakage characterization data in section 5.3, correcting units of measurement. modi fied footnote 1 under section 5.10. changed product family numbering from cs497xx to cs4970x4. corrected product listings in table under section 5.9 ?switching c haracteristics ? internal clock? on page 12 . pp7 september 30, 2008 removed references to external parallel flash / sram interface. pp8 november 6, 2009 updated the feature descriptions on the first page of this data sheet. removed references to uart port. removed references to 11.2896, 18.432, and 27 mhz frequency clocks in note 1 in section 5.8 ?switching ch aracteristics ? xti? on page 11 and the min and max external crysta l operating frequency values in that same section. added section 5.6 ?thermal data (128-pin lqfp)? on page 10 . updated figure 9 and figure 10 . updated (now removed) section. updated figure 15 and figure 16 . in section 5.3, the parameter, ?input leakage current (all digital pins with internal pull-up resistors enabl ed, and xti)?, max value changes from 50 ma to 70 ma. in section 5.13, the para meter scp_clk low to scp_sda out valid with symbol ?tiicdov? max value changes fr om 18 ns to 36 ns. added cs497014 to section 6 ?ordering information? on page 25 and to section 7 ?environmental, manufacturing, and handling information? on page 26 . updated table 2, ?device and firmware selection guide,? on page 5 . pp9 november 2, 2010 added ?status? column and footnote 1 to ta b l e 4 . pp10 march 25, 2011 added tj conditions to section 5.2 . changed 500 ma to 350 ma in section 5.4 . updated section 5.16 ?switching characteristics ? digital audio slave input port? on page 20 . updated section 5.17 ?switching characteristics ? digital audio output port? on page 21 .
cs4970x4 data sheet 32-bit high definition audio decoder dsp family ds752pp10 32 contacting cirrus logic support for all product questions and inquiries cont act a cirrus logic sales representative. to find the one nearest to you go to www.cirrus.com . important notice cirrus logic, inc. and its subsidiaries (?cirrus?) believe that the information contained in this document is accurate and reli able. however, the information is subject to change without notice and is provided ?as is? without warranty of any kind (express or implied). customers are advised to obtai n the latest version of relevant infor- mation to verify, before placing orders, that information being relied on is current and complete. all products are sold subjec t to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. no r esponsibility is assumed by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringeme nt of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights associated with the information con tained herein and gives consent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other product s of cirrus. this consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for re sale. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe proper- ty or environmental damage (?critical ap plications?). cirrus products are not desi gned, authorized or warranted for use in products surgically implan ted into the body , automotive safety or se curity devices, life support products or other critical applications. inclusio n of cirrus products in such appl ications is understood to be fully at the customer's risk and cirrus disclaims and makes no warranty, express, statutory or implie d, including the implied warran ties of merchantability and fit- ness for particular purpos e, with regard to any cirrus product that is used in such a manner . if the customer or customer's customer uses or permits the use of cirrus products in cri tical applications, customer agrees, by such use, to fully indem- nify cirrus, its officers, directors, emplo yees, distributors and other agents from any and all liability, including attorneys' fees and costs, that may result from or arise in connectio n with these uses. cirrus logic, cirrus, cirrus logic logo designs, dsp composer, dsp condenser, and clide are trademarks of cirrus logic, inc. thx is a registered trademark of thx, ltd. thx se lect 2 and thx ultra 2 are trademarks of thx, ltd. aac, ac-3, audistry, dolby, dolby digital, dolby digital plus, dolby truehd, dolby volume, dolby headphone 2, dolby virtual spe aker 2, pro logic, surround ex, are either trademarks or registered trademarks of dolby laboratories, inc. supply of an implementation of dolby technology does not convey a license nor imply a right under any patent, or any other industrial or intellectual property right of dolby laboratories, to use the implementation in any finished end-user or ready-to-use final product. it is hereby notified that a license for such use is required from dolby laboratories. dts, dts digital surround, and dts-hd are registered trademarks of the digital theater systems, inc. dts neo:6, dts-es 96/24, d ts-es, dts 6.1, dts 96/24, dts neural surround, and dts express are trademarks of digital theater systems, inc. it is hereby notified that a third-party l icense from dts is necessary to dis- tribute software of dts in any finished end-user or ready-to-use final product. srs, srs 3d, srs cs auto, srs cs headphone, srs circle cinema 3d , srs circle surround, srs circle surround ii, srs geq, srs har dlimiter, srs head- phone, srs headphone 360, srs hpf, srs studiosound hd, srs trueq, srs trumedia, srs trusurround, srs trusurround xt, srs trusur round hd, srs trusurround hd4, srs truvolume, srs vip+, srs wow, srs wow xt, srs wow hd are either trademarks or registered trademarks of srs labs, inc. srs, srs 3d, srs cs auto, srs cs headphone, srs circle cinema 3d, sr s circle surround, srs circle surround ii, srs geq, srs hardlimi ter, srs headphone, srs headphone 360, srs hpf, srs studiosound hd, srs trueq, srs trumedia, srs trusurround, srs trusurround xt, srs trusurround h d, srs trusur- round hd4, srs truvolume, srs vip+, srs wow, srs wow xt, srs wow hd technologies are incorporated under license from srs labs, inc. srs, srs 3d, srs cs auto, srs cs headphone, srs circle cinema 3d, srs circle surround, srs circle surround ii, srs geq, srs hardlimiter, srs headphone, srs head- phone 360, srs hpf, srs studiosound hd, srs trueq, srs trumedia, srs trusurround, srs trusurround xt, srs trusurround hd, srs t rusurround hd4, srs truvolume, srs vip+, srs wow, srs wow xt, srs wow hd technologies incorporated in the cirrus logic cs497xxx products are ow ned by srs labs, a u.s. corporation and licensed to cirrus logic, inc. purchaser of cirrus logic cs497xxx products must sign a license for use o f the chip and display of the srs labs trademarks. any products incorporating the cirrus logic cs497xxx products must be sent to srs labs for review. srs, srs 3d, srs cs auto, srs cs headphone, srs circle cinema 3d, srs circle surround, srs circle surround ii, srs geq, srs hardlimiter, srs headphone, srs headphone 360, srs hpf, srs studio- sound hd, srs trueq, srs trumedia, srs trusurround, srs trusu rround xt, srs trusurround hd, srs trusurround hd4, srs truvolume, srs vip+, srs wow, srs wow xt, srs wow hd technologies are protected under us and foreign patents issued and/or pending. neither the purchase of the cirrus logic cs497xxx products, nor the corresponding sale of audio enhancement equipment conveys the right to sell commercialized recording s made with any srs technolo- gy/solution. srs labs requires all set makers to comply with all rules and regulations as outlined in the srs trademark usage m anual. microsoft and windows media are registered trademarks of microsoft corporation. the product includes technology owned by micros oft corporation and cannot be used or distributed without a license from microsoft licensing, inc. motorola and spi are trademarks of motorola, inc. intel is a registered trademark of intel corporation. i 2 c is a trademark of philips semiconductor. all other brand and product names in this document may be trademarks or service marks of their respective owners.

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